An Efficient Design of 3bit and 4bit Flash ADC
نویسندگان
چکیده
منابع مشابه
Design of CMOS Comparators for FLASH ADC
The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, ...
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چکیده ندارد.
Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology
ABSTRACT This paper presents a design of a high speed Comparator design using 65nm digital CMOS technology on Cadence Virtuoso Design Tool. The proposed FLASH ADC Design consists of fully differential topology. The first stage provides a Voltage Divider circuit and the second stage is Comparator Design having high sampling frequency tolerance, and the high efficient common drain circuit provide...
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In this paper, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1GHz, is implemented in a 1.2 V analog supply voltage. HSpice simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes less power i n a commercial 90n...
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The performance of Flash Analogto-Digital converter is greatly influenced by the choice of Comparator and Thermometer-toBinary encoder design. The work describes the design and pre-simulation of a , 3bit and an 4bit analog to digital converter for low power CMOS. It requires 2-1 comparators, an encoder to convert thermometer code to binary code. The design is simulated in cadence environment us...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2013
ISSN: 0975-8887
DOI: 10.5120/9974-4802